Microprocessor devices fabricated with current CMOS technology are designed with great care to comprehend the circuit performance variations due to process shifts from one tolerance extreme to the other. Designers have become accustomed to speak of MOS transistors having maximum drive capability as strong transistors and MOS transistors with minimum drive capability as weak transistors. At both of these extremes, the transistors are within specified process tolerance limits, and it is desirable to maximize the useable yield of all functional devices even though different speed performance devices will be produced. Normally the salability of the whole performance distribution is not difficult to establish.
In practice, designs are analyzed by (a) transistor strength, (b) power supply voltage tolerances, (c) interconnect resistance and capacitance and (d) operating temperature, among other possible parameters. Logic circuits must match as closely as possible the memory and the interfacing should be optimized on every die in as much as practical.
Experience indicates that I/O designs should be subjected to rather stringent minimum-maximum propagation delay limits to assure proper interface functioning between the outputs of a transmitting chip and the inputs of a receiving chip. Latching elements are present at both the signal source and signal destination and set-up time and hold-time requirements must be met to assure desired performance. Therefore, on a given integrated circuit the specifications for maximum set-up time and maximum hold time at critical inputs that must be tightly controlled. Often the degree of control the design can provide is insufficient to allow the entire distribution of circuit performance to meet the critical design parameters. In these cases techniques to adjust the performance of critical input/output functions provides a means to improve yield.
Design/Fabrication/Test Methodology
Traditionally, critical I/O timing specifications make it necessary for designers to comprehend all of the following design characteristics” (a) I/O interface design/architecture; (b) simplified clock distribution; (c) master/slave protocols; (d) self-clocking techniques including the use of analog or digital phase locked loop functions to create alignments between I/O circuit & process; (e) I/O buffers designed for low voltage-temperature performance variation; (f) rigid process controls; (g) I/O test screening; and (h) speed sort parts by I/O speeds/application. All these design and application considerations involve sophisticated design/process practices and/or compromises in design/process.
Previous Techniques for Optimal I/O Interface Performance
Originally, I/O performance matching was achieved by altering the number of gates in a delay path by adding or removing gates in a revision of the chip interconnect pattern. This approach incurs significant costs and cycle times to produce revised photomask reticles and to complete fabrication of the revised product.
A later technique of I/O performance adjustment employed laser fuses. Laser fuses built into the die may be blown to achieve many of the desired I/O timing adjustments. However, laser fuses must be large in chip area to ensure dependable and successful laser beam hit.
Electrical Fuses for Programming
Electrical fuses (eFuses) are extremely attractive for this kind of application. Such eFuses have made a great impact on digital processor devices. Originally eFuses were applied to the obvious needs for device programmability. The possibility of programming a device to do a specific task efficiently has made modest cost special purpose processors a reality. Many fusible interconnect links are constructed of materials such as deposited amorphous polysilicon.
In the prior art electrical fuses (eFuses) in VLSI silicon devices are programmed by applying a relatively large amount of power to the fuse body to melt and separate the fuse body. This changes the eFuse resistance from a low pre-blow resistance to a high post-blow resistance. This result can be sensed to determine the state of the eFuse: unblown or blown.
eFuse Implementation
The eFuse for a conventional programmable device application is normally configured as a chain or two-dimensional array containing sometimes hundreds of eFuses and supporting logic. Several definitions will be helpful in clarifying the descriptions of eFuse implementation to follow.
An eFuse is a circuit element, which has a natural un-programmed state, but may be permanently programmed to the opposite state. An eFuse element includes an eFuse along with its programming and sensing circuits. An eFuse cell includes an eFuse element plus the local logic required to integrate it into an eFuse chain. An eFuse chain is one or more eFuse cells connected in series or arrays. An eFuse controller is comprised of the control logic designed to access the eFuse chains or arrays. An un-programmed eFuse has a pre-defined maximum low resistance value. A programmed eFuse has a pre-defined minimum high resistance value. An eFuse chain is programmed by loading the desired fused state and non-fused state locations into a programming database containing a record for the individual elements of the entire chain. Then those values are sequentially programmed into each eFuse.
FIG. 1 illustrates the conventional eFuse cell circuit configuration. This includes eFuse element 101 plus the local logic required to integrate it into an eFuse chain. This logic includes a CData flip-flop 103 that is clocked by the Enable Clock 108 and stores cell data in the chain. The logic further includes a PData flip-flop 102 that is clocked by the Data Clock 106 and latches program data being passed into the eFuse cell.
In the program mode, incoming PData In 107 is latched into the PData flip-flop 102 and programmed into the eFuse element on the occurrence of one or more program pulses initiated at Program input 110. PData Out passes to the eFuse cell via path 116. In the program mode PData Out is passed through multiplexers 104 and 105 and is latched into the CData flip-flop 102. The voltage VPP 109 is the programming power source. Program data is passed serially to the next cell in the chain at PData Out line 116.
In the test mode, the CData flip-flop 103 latches the data from the present cell and passes it to Cell Data Out 115. This data from the present cell is passed through multiplexer 104 and multiplexer 105 as directed by the Test input 111.
Initz input 112 acts to initialize all flip-flops in the cell chain prior to the programming cycle. Margin input 114 allows adjustment to the reference input for a differential amplifier so that the desired high resistance values specified for a program element may be modified.
FIG. 2 illustrates a simplified view of a conventional eFuse system having an eFuse controller 200 and a number of series-connected eFuse cells 201 through 205. Each eFuse cell 201 through 205 has the local logic of FIG. 1 for integrating the cells into an eFuse array. Cell 201 differs however in that it provides storage for a burned-in die identifier (die I.D.). At the last stage of the array 205 PData Out 208 and CData Out 209 are passed back to the controller as required in the program and test modes. The nodes labeled Cell Out (e.g. 206 and 207) provide a single bit digital output representing the state of that cell, both in the programmed state and in the soft test state. The soft test state provides a non-permanent condition that emulates the state that would have been established after the fuse is programmed.
I/O Design Parameters and Specifications
The critical I/O timing specifications consist of the following timing parameters: tpdmin the minimum propagation delay for signal data output; tpdmax the maximum propagation delay for signal data output; tisetupmin the minimum setup time for data input signal; and tiholdmin the minimum hold time for data input signal. These timing specifications must be met in each of the nine design analysis corners listed in Table 1.
TABLE 1Design Analysis CornersCoreI/OTempMetalCornerVoltageVoltageCelsiusR/C11.203.3025typical21.203.3025typical31.083.00105maximum41.263.00105maximum51.323.60−40minimum61.473.60−40minimum71.985.0025minimum80.681.1025minimum91.704.60140minimumTypically there is also a requirement for adequate guard band tolerances to account for correlation between test machines and for stability of values measured in repetitive tests.